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-- Company: 
-- Engineer:
--
-- Create Date:   16:32:08 07/26/2009
-- Design Name:   
-- Module Name:   C:/Education/SENG_440/jeffngilesrsaopt/montgomery_multiplier/mont_mult/mont_mult_test.vhd
-- Project Name:  mont_mult
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: mont_mult
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
 
ENTITY mont_mult_test IS
END mont_mult_test;
 
ARCHITECTURE behavior OF mont_mult_test IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT mont_mult
    PORT(
         a : IN  std_logic_vector(1023 downto 0);
         b : IN  std_logic_vector(1023 downto 0);
         n : IN  std_logic_vector(1023 downto 0);
         clk : IN  std_logic;
			i_out : out integer;
         s : OUT  std_logic_vector(2047 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal a : std_logic_vector(1023 downto 0) := (others => '0');
   signal b : std_logic_vector(1023 downto 0) := (others => '0');
   signal n : std_logic_vector(1023 downto 0) := (others => '0');
   signal clk : std_logic;

 	--Outputs
   signal s : std_logic_vector(2047 downto 0);
	signal i_out : integer;

   -- Clock period definitions
   constant clk_period : time := 1us;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: mont_mult PORT MAP (
          a => a,
          b => b,
          n => n,
          clk => clk,
			 i_out => i_out,
          s => s
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100ms.
      --wait for 100ms;	

      wait for clk_period*10;

      -- insert stimulus here
		a <= (others => '0');
		b <= (others => '0');
		n <= (others => '0');

      wait;
   end process;

END;
